1. Field of the Invention
The present invention is related to manufacturing data analysis and more particularly to semiconductor process manufacturing data analysis.
2. Background Description
Typically, integrated circuit chips are manufactured by forming a grid of chips clustered onto a single semiconductor wafer, e.g., a silicon wafer. The grid may have a thousand or more chip (die) sites or locations. Chip patterns may be formed on the wafer photolithographically, layer by layer. Once all of the layers have been formed the wafer, it is diced to separate the individual chips (die). Furthermore, groups of 20 or more wafers are normally formed more or less at the same time. Each of these groups is called a lot. Ideally, every chip on each wafer in every lot forms identically with every other chip on every other wafer in every other lot, such that all chips of the same chip type are identical. However, realistically, no two chips are identical. Chip parameters always exhibit some lot by lot variation, as well as wafer by wafer variation within a lot and, chip by chip on each wafer.
Modern semiconductor manufacturing processes are very complex, perhaps, including hundreds of individual process steps from selecting a blank wafer, to forming the layers, to producing the final working product. Manufacturing engineers use various test and metrology tools throughout the process to collect a wide assortment of data on each of these process steps and on the resulting products. These tests measure a wide variety of parameters, encompassing many types of electrical, physical, mechanical and chemical traits, both of the manufacturing process and the product. The parameters include semiconductor process data and measure variations that may be analyzed to identify the source of these variations, whether from the tools, recipes, people, etc. This measurement data is analyzed in an attempt to qualitatively and quantitatively define various relationships, e.g., how the measured parameters affect the performance and quality of the products produced.
Normally, these parameters describe the performance and physical characteristics of semiconductor products and, generally, can only be collected from finished product resulting from, potentially, hundreds of separate processing steps. In addition with multiple tools used at each process step, each tool adding some parametric variation, it is no surprise that the combined influence of all of these independent variations on different parameters makes isolating any one out-of-spec source difficult. Very often, prior art approaches identified numerous false positive and false negatives. A straight forward statistical analysis approach isolates significant data from one source at a time by sorting the data such that all other potential sources are common for each sort. This “divide and conquer” approach divides the entire population into subgroups that each may contain too few points for the statistical tools to discern differences of any real meaning.
For example, a Product Engineer (PE) may have product that fails to meet customer's performance requirements, i.e., the product is “out-of-spec.” The PE must be able to identify and, if possible, isolate chip/process parameters measured at wafer sort or final test that correlate to the failure. Then, the PE must take appropriate action at the identified source of the failure to tighten the variation of chip/process parameters to produce product that once again conforms with the customer's requirements. Additionally, even if the product is “in-spec,” currently, the only way to assure that it remains in-spec may be to limit process parameter variation, thereby limiting drift towards process window edges, where performance may degrade. So, for example, product that is performance sorted may fall short e.g., at process window edges. The challenge for the PE is to identify variances from natural groupings of the process flow data that may be arising from different sources, i.e., different test facilities, different tools used at the same step, etc. Once identified, these variances may be corrected to remove or minimize parametric variation. Intelligently analyzing this process data, whether manually or automatically, is critical for the PE. Typically, the PE must confront two data analysis issues.
First, normally, all the “raw” chip level data (die level data) is considered as a whole as randomly generated. However, the data points are seldom independent of each other. At various stages throughout the manufacturing process, data for numerous chips may be related. Die 1 on wafer 1 in lot 1 cannot be run on a separate tool than die 2 on wafer 1 in lot 1. Die from the same wafer are manufactured more or less simultaneously and in parallel. Wafers from each lot are grouped together for step by step processing. At different steps wafers from the same lot may be subdivided/processed on different equipment and then, intermixed or recombined. However, traditionally, all of the wafer data from each lot and, even from several lots, is combined and collapsed into a few simple lot level statistics (e.g., a lot mean and a lot standard deviation) that are used for process analysis.
Second, once the process data is collected and differences are resolved statistically, information that data must be related back to the process sequence without false positive or false negative identification errors. There are, primarily, two sources of these errors. First, since there are so many process steps and because the targeted parameter differences may be so small, a huge amount of data may be necessary to statistically correlate the results. Second, lots and wafers within each lot are not randomly processed. Instead, wafers are somewhat methodically grouped and processed on tools available at each processing step. Consider for example, a simple processing matrix of 3 steps with 3 tools available at each step. If one of the three possible tools is “bad” at step 1; then, it should not be assumed that the lots run on this bad tool are thoroughly and randomly mixed with lots from each of the other 2 tools for subsequent processing at step 2 amongst the three possible tools for that step. Otherwise, making such an assumption would result in a false difference from the statistical comparison of the lot data among the three tools at step 2 where in actuality none exists. The traditional divide and conquer solution was to select only data for step 1 in which the combinations at all other steps are uniform (i.e. all through the same tool at each of step 2, 3, etc.). This restriction greatly reduces the amount of available data, exacerbating the need for large amounts of data for analysis.